One of the continuing goals of the semiconductor industry is the production of smaller microelectronic devices and denser integrated circuits. In order to produce microelectronic devices having dimensions which are small enough to meet the requirements of Ultra Large Scale Integration (ULSI), both the lateral and vertical dimensions of the microelectronic devices in a semiconductor substrate must be reduced. In particular, as the device sizes shrink, there is a need to form shallow regions of a predetermined conductivity at the face of the semiconductor substrate. These shallow regions, currently less than about fifteen hundred Angstroms in depth, can be used to form p-n junctions with the semiconductor substrate or with other regions in the semiconductor substrate. For example, there is a need to form shallow source and drain regions of a Field Effect Transistor (FET).
Presently, shallow regions are formed at the face of a semiconductor substrate by ion implantation. As is well known to those having skill in the art, ion implantation is a process in which appropriate dopant atoms are ionized, accelerated and directed at the face of the semiconductor substrate, so that the accelerated ions bombard and become implanted in the semiconductor substrate. Ion implantation typically results in implantation of p-type or n-type dopants on the entire semiconductor substrate. However, by using masks defined by well known lithographic techniques, patterned regions of implanted ions may be formed in the semiconductor substrate. Silicon dioxide is typically used as a mask, although other well known masks can also be used.
For example, to form an FET, field oxide regions are typically formed at the face of the semiconductor substrate, surrounding a predetermined area on the face. A gate electrode is then formed on the predetermined area. Ion implantation is then used to implant p-type or n-type dopants on the exposed face of the substrate, between the field oxide and gate electrode, to form the source and drain regions.
Unfortunately, ion implantation damages the face of the substrate, due to displacement of the lattice atoms in the substrate by the accelerated ions. This damage is often referred to as "implant damage". In many cases, the degree of lattice displacement can be enough to completely destroy the monocrystalline nature of the semiconductor substrate face. Implant damage is particularly objectionable for shallow regions formed at the substrate face because a large portion of the shallow region may be damaged.
The damage caused by ion implantation can be reduced by subjecting the wafer to a high temperature (for example above 850.degree. C.) anneal in a furnace for an extended period of time. Annealing causes recrystallization of the substrate. However, a high temperature extended time anneal cannot eliminate all implantation damage. Moreover, the high temperature anneal also causes further diffusion of the implanted ions within the substrate, and thereby precludes the formation of shallow junctions at the substrate face. Accordingly, the conventional process for forming a doped region, by ion implantation and a subsequent anneal, is incompatible with the formation of ultra shallow doped regions.
Another critical concern in forming smaller microelectronic devices is the formation of electrical contacts to the shallow doped regions thereof. For example, when small geometry source and drain regions are formed at the face of a semiconductor substrate, electrical contact to these regions must be established in order to produce a functional FET. Since the contact areas of these regions are very small, it is difficult to form low resistivity contacts to these regions. When an ohmic (non-rectifying) contact is formed between a metal and a semiconductor, it is important to obtain the smallest possible contact resistance. This resistance is a function of the contact area as well as the energy band structure of the metal deposited on the semiconductor substrate.
In order to effectively contact small regions, a self-aligned silicide process, often referred to as a "salicide" process, has been developed. As known to those having skill in the art, silicidation is the process of forming a metal-silicon compound for use as an electrical contact. The process is desirable because the resulting silicide typically has a lower resistivity than does silicon alone and can be self aligned to exposed regions of silicon. Silicidation is often carried out by depositing a metal such as titanium, cobalt or tungsten onto silicon, followed by either conventional furnace annealing or rapid thermal annealing to form the metal silicide.
The salicide process provides a silicide contact without requiring alignment of the contact to the underlying region. In the salicide process, a layer of silicide-forming metal is blanket-deposited over the semiconductor substrate. Upon annealing at about 600.degree. C., the metal reacts with the underlying silicon but does not react with the underlying silicon dioxide mask or gate electrode wall. Accordingly, a metal-silicon compound is formed on the exposed face of the semiconductor substrate, but not on the wall of the gate electrode or on the field oxide. The unreacted metal may then be removed from the gate electrode wall and field oxide using conventional etching techniques. Typical etchants combine hydrogen peroxide with sulfuric acid or ammonium hydroxide. A final, relatively higher temperature anneal may then be performed at about 800.degree. C. to lower the resistivity of the silicide. Electrical contacts, for example to the source and drain regions of a FET, are thereby formed without requiring a separate lithography step.
Unfortunately, the salicide process can also adversely impact the formation of shallow regions in the substrate. In particular, the salicide process causes a significant amount of silicon to be consumed at the substrate face. As described above, the metal silicide is formed from the chemical reaction between the deposited metal and the underlying silicon. This typically unavoidably results in consumption of the silicon at the substrate face. As an illustrative example, when a 10 nm layer of titanium is deposited and then annealed to form titanium silicide, approximately 25 nm of silicon will also be consumed. This means that a shallow 75 nm region will be totally consumed by a titanium layer 30 nm thick used to produce titanium silicide.
A potential solution to this problem has been to selectively deposit additional silicon (typically monocrystalline silicon) on the substrate face over the source and drain regions. The additional silicon forms a buffer or sacrificial layer between the substrate and the metal deposited to form the silicide. This process raises the source and drain junctions and results in what is sometimes referred to as an "elevated" or "raised" source and drain FET. Unfortunately, this process possesses other disadvantages. Selective deposition of silicon requires relatively high temperatures (typically greater than 800.degree. C.) and may employ or produce hydrochloric acid (HCl) which in turn may damage the structure. Also, dopant diffusion often takes place at the temperature required to deposit the silicon layer, making the junction deeper.
Accordingly, Ultra Large Scale Integration requires a process for forming doped regions at the face of a semiconductor substrate, which eliminates the need for ion implantation and the resulting substrate damage. This process should preferably be compatible with a salicide process for contacting the doped regions, and preferably allows the salicide process to be implemented without adversely impacting the reduced geometry doped regions which are formed.